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? 2009 microchip technology inc. ds22147a-page 1 MCP4017/18/19 features ? potentiometer or rheostat configuration options ? 7-bit: resistor network resolution - 127 resistors (128 steps) ? zero scale to full scale wiper operation ?r ab resistances: 5 k , 10 k , 50 k , or 100 k ? low wiper resistance: 100 (typical) ? low tempco: - absolute (rheostat): 50 ppm typical (0c to 70c) - ratiometric (potentiometer): 10 ppm typical ?simple i 2 c protocol with read & write commands ? brown-out reset protection (1.5v typical) ? power-on default wiper setting (mid-scale) ? low-power operation: - 2.5 a static current (typical) ? wide operating voltage range: - 2.7v to 5.5v - device characteristics specified - 1.8v to 5.5v - device operation package types ? wide bandwidth (-3 db) operation: - 2 mhz (typical) for 5.0 k device ? extended temperature range (-40c to +125c) ? very small package (sc70) ? lead free (pb-free) package device features mcp4018 sc70-6 mcp4019 sc70-5 rheostat 4 1 2 3 5 w sda v dd v ss scl 4 1 2 3 6 a sda v dd v ss scl 5 w a w w a b b potentiometer MCP4017 sc70-6 4 1 2 3 6 w sda v dd v ss scl 5 b a w b device control interface # of steps wiper configuration memory type resistance (typical) vdd operating range (1) package options (k ) wiper ( ) MCP4017 i 2 c 128 rheostat ram 5.0, 10.0, 50.0, 100.0 75 1.8v to 5.5v sc70-6 mcp4018 i 2 c 128 potentiometer ram 5.0, 10.0, 50.0, 100.0 75 1.8v to 5.5v sc70-6 mcp4019 i 2 c 128 rheostat ram 5.0, 10.0, 50.0, 100.0 75 1.8v to 5.5v sc70-5 note 1: analog characteristics only tested from 2.7v to 5.5v 7-bit single i 2 c? digital pot with volatile memory in sc70
MCP4017/18/19 ds22147a-page 2 ? 2009 microchip technology inc. device block diagram comparison of similar microchip devices (1) device control interface # of steps wiper configuration memory type resistance (typical) v dd operating range (2) hv interface wiperlock technology package options (k ) MCP4017 i 2 c 128 rheostat ram 5.0, 10.0, 50.0 , 100.0 1.8v to 5.5v no no sc70-6 mcp4012 u/d 64 rheostat ram 2.1, 5.0, 10.0, 50.0 1.8v to 5.5v yes no sot-23-6 mcp4022 u/d 64 rheostat ee 2.1, 5.0, 10.0, 50.0 2.7v to 5.5v yes yes sot-23-6 mcp4132 spi 129 rheostat ram 5.0, 10.0, 50.0, 100.0 1.8v to 5.5v yes no pdip-8, soic-8, msop-8, dfn-8 mcp4142 spi 129 rheostat ee 5.0, 10.0, 50.0, 100.0 2.7v to 5.5v yes yes mcp4152 spi 257 rheostat ram 5.0, 10.0, 50.0, 100.0 1.8v to 5.5v yes no mcp4162 spi 257 rheostat ee 5.0, 10.0, 50.0, 100.0 2.7v to 5.5v yes yes mcp4532 i 2 c 129 rheostat ram 5.0, 10.0, 50.0, 100.0 1.8v to 5.5v yes no msop-8, dfn-8 mcp4542 i 2 c 129 rheostat ee 5.0, 10.0, 50.0, 100.0 2.7v to 5.5v yes yes mcp4552 i 2 c 257 rheostat ram 5.0, 10.0, 50.0, 100.0 1.8v to 5.5v yes no mcp4562 i 2 c 257 rheostat ee 5.0, 10.0, 50.0, 100.0 2.7v to 5.5v yes yes mcp4018 i 2 c 128 potentiometer ram 5.0, 10.0, 50 .0, 100.0 1.8v to 5.5v no no sc70-6 mcp4013 u/d 64 potentiometer ram 2.1, 5.0, 10.0, 50.0 1.8v to 5.5v yes no sot-23-6 mcp4023 u/d 64 potentiometer ee 2.1, 5.0, 10.0, 50.0 2.7v to 5.5v yes yes sot-23-6 mcp4019 i 2 c 128 rheostat ram 5.0, 10.0, 50.0 , 100.0 1.8v to 5.5v no no sc70-5 mcp4014 u/d 64 rheostat ram 2.1, 5.0, 10.0, 50.0 1.8v to 5.5v yes no sot-23-5 mcp4024 u/d 64 rheostat ee 2.1, 5.0, 10.0, 50.0 2.7v to 5.5v yes yes sot-23-5 note 1: this table is broken into three groups by a thick line (and color coding). the unshaded devices in this table are the devices described in this data sheet, while th e shaded devices offer a comparable resistor network configuration. 2: analog characteristics only tested from 2.7v to 5.5v power-up/ brown-out control v dd v ss i 2 c serial interface module, control logic, & resistor network 0 (pot 0) scl sda a (2) w b (1, 2) note 1 note 1: some configurations will have this signal internally connected to ground. 2: in some configurations, this signal may not be connected externally memory (internally floating or grounded).
? 2009 microchip technology inc. ds22147a-page 3 MCP4017/18/19 1.0 electrical characteristics absolute maximum ratings ? voltage on v dd with respect to v ss ..... -0.6v to +7.0v voltage on scl, and sda with respect to v ss ............................................................................. -0.6v to 12.5v voltage on all other pins (a, w, and b) with respect to v ss ............................ -0.3v to v dd + 0.3v input clamp current, i ik (v i < 0, v i > v dd , v i > v pp on hv pins) ........... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ....................................... 20 ma maximum output current sunk by any output pin ........................................................................... 25 ma maximum output current sour ced by any output pin ........................................................................... 25 ma maximum current out of v ss pin ...................... 100 ma maximum current into v dd pin ......................... 100 ma maximum current into a, w and b pins........... 2.5 ma package power dissipation (t a = +50c, t j = +150c) sc70-5 ............................................................ 302 mw sc70-6 .................................................................. tbd storage temperature .......................... -65c to +150c ambient temperature with power applied ........................................................... -40c to +125c esd protection on all pins ........................ 4 kv (hbm) ............................................................... ......... 400v (mm) maximum junction temperature (t j ) .............. +150c ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any ot her conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
MCP4017/18/19 ds22147a-page 4 ? 2009 microchip technology inc. ac/dc characteristics dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specif ied operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions supply voltage v dd 2.7 ? 5.5 v analog characteristics specified 1.8 ? 5.5 v digital characteristics specified v dd start voltage to ensure wiper reset v bor ? ? 1.65 v ram retention voltage (v ram ) < v bor v dd rise rate to ensure power-on reset v ddrr ( note 7 )v/ms delay after device exits the reset state (v dd > v bor ) t bord ?1020s supply current (note 8) i dd ? 45 80 a serial interface active, write all 0?s to volatile wiper v dd = 5.5v, f scl = 400 khz ? 2.5 5 a serial interface inactive, (stop condition, scl = sda = v ih ), wiper = 0, v dd = 5.5v note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4018 device only, includes v wzse and v wfse . 4: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 5: this specification by design. 6: non-linearity is affected by wiper resistance (r w ), which changes signific antly over voltage and temperature. 7: por/bor is not rate dependent. 8: supply current is independent of current through the resistor network
? 2009 microchip technology inc. ds22147a-page 5 MCP4017/18/19 resistance ( 20%) r ab 4.0 5 6.0 k -502 devices (note 1) 8.0 10 12.0 k -103 devices (note 1) 40.0 50 60.0 k -503 devices (note 1) 80.0 100 120.0 k -104 devices (note 1) resolution n 128 taps no missing codes step resistance r s ?r ab / (127) ? note 5 wiper resistance r w ? 100 170 v dd = 5.5 v, i w = 2.0 ma, code = 00h ? 155 325 v dd = 2.7 v, i w = 2.0 ma, code = 00h nominal resistance te m p c o r ab / t ? 50 ? ppm/c t a = -20c to +70c ? 100 ? ppm/c t a = -40c to +85c ? 150 ? ppm/c t a = -40c to +125c ratiometeric te m p c o v wb / t ? 15 ? ppm/c code = midscale (3fh) resistor terminal input voltage range (terminals a, b and w) v a, v w, v b vss ? v dd v note 4, note 5 maximum current through terminal (a, w or b) note 5 i t ? ? 2.5 ma terminal a i aw , w = full scale (fs) ? ? 2.5 ma terminal b i bw , w = zero scale (zs) ? ? 2.5 ma terminal w i aw or i bw , w = fs or zs ? ? 1.38 ma terminal a and terminal b i ab , v b = 0v, v a = 5.5v, r ab(min) = 4000 ? ? 0.688 ma i ab , v b = 0v, v a = 5.5v, r ab(min) = 8000 ? ? 0.138 ma i ab , v b = 0v, v a = 5.5v, r ab(min) = 40000 ? ? 0.069 ma i ab , v b = 0v, v a = 5.5v, r ab(min) = 80000 ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specif ied operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4018 device only, includes v wzse and v wfse . 4: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 5: this specification by design. 6: non-linearity is affected by wiper resistance (r w ), which changes signific antly over voltage and temperature. 7: por/bor is not rate dependent. 8: supply current is independent of current through the resistor network
MCP4017/18/19 ds22147a-page 6 ? 2009 microchip technology inc. full scale error ( mcp4018 only) (code = 7fh) v wfse -3.0 -0.1 ? lsb 5 k 2.7v v dd 5.5v -2.0 -0.1 ? lsb 10 k 2.7v v dd 5.5v -0.5 -0.1 ? lsb 50 k 2.7v v dd 5.5v -0.5 -0.1 ? lsb 100 k 2.7v v dd 5.5v zero scale error ( mcp4018 only) (code = 00h) v wzse ? +0.1 +3.0 lsb 5 k 2.7v v dd 5.5v ? +0.1 +2.0 lsb 10 k 2.7v v dd 5.5v ? +0.1 +0.5 lsb 50 k 2.7v v dd 5.5v ? +0.1 +0.5 lsb 100 k 2.7v v dd 5.5v potentiometer integral non-linearity inl -0.5 0.25 +0.5 lsb 2.7v v dd 5.5v mcp4018 device only (note 2) potentiometer differential non- linearity dnl -0.25 0.125 +0.25 lsb 2.7v v dd 5.5v mcp4018 device only (note 2) bandwidth -3 db (see figure 2-83 , load = 30 pf) bw ? 2 ? mhz 5 k code = 3fh ?1?mhz10k code = 3fh ? 260 ? khz 50 k code = 3fh ? 100 ? khz 100 k code = 3fh ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specif ied operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4018 device only, includes v wzse and v wfse . 4: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 5: this specification by design. 6: non-linearity is affected by wiper resistance (r w ), which changes signific antly over voltage and temperature. 7: por/bor is not rate dependent. 8: supply current is independent of current through the resistor network
? 2009 microchip technology inc. ds22147a-page 7 MCP4017/18/19 rheostat integral non-linearity mcp4018 ( note 3 ) MCP4017 and mcp4019 devices only (note 3) r-inl -2.0 0.5 +2.0 lsb 5 k 5.5v, i w = 900 a -5.0 +3.5 +5.0 lsb 2.7v, i w = 430 a ( note 6 ) see section 2.0 lsb 1.8v ( note 6 ) -2.0 0.5 +2.0 lsb 10 k 5.5v, i w = 450 a -4.0 +2.5 +4.0 lsb 2.7v, i w = 215 a ( note 6 ) see section 2.0 lsb 1.8v ( note 6 ) -1.125 0.5 +1.125 lsb 50 k 5.5v, i w = 90 a -1.5 +1 +1.5 lsb 2.7v, i w = 43 a ( note 6 ) see section 2.0 lsb 1.8v ( note 6 ) -0.8 0.5 +0.8 lsb 100 k 5.5v, i w = 45 a -1.125 +0.25 +1.125 lsb 2.7v, i w = 21.5 a ( note 6 ) see section 2.0 lsb 1.8v ( note 6 ) rheostat differential non- linearity mcp4018 ( note 3 ) MCP4017 and mcp4019 devices only (note 3) r-dnl -0.5 0.25 +0.5 lsb 5 k 5.5v, i w = 900 ma -0.75 +0.5 +0.75 lsb 2.7v, i w = 430 a ( note 6 ) see section 2.0 lsb 1.8v ( note 6 ) -0.5 0.25 +0.5 lsb 10 k 5.5v, i w = 450 a -0.75 +0.5 +0.75 lsb 2.7v, i w = 215 a ( note 6 ) see section 2.0 lsb 1.8v ( note 6 ) -0.375 0.25 +0.375 lsb 50 k 5.5v, i w = 90 a -0.375 0.25 +0.375 lsb 2.7v, i w = 43 a ( note 6 ) see section 2.0 lsb 1.8v ( note 6 ) -0.375 0.25 +0.375 lsb 100 k 5.5v, i w = 45 a -0.375 0.25 +0.375 lsb 2.7v, i w = 21.5 a ( note 6 ) see section 2.0 lsb 1.8v ( note 6 ) capacitance (p a )c aw ? 75 ? pf f =1 mhz, code = full scale capacitance (p w )c w ? 120 ? pf f =1 mhz, code = full scale capacitance (p b )c bw ? 75 ? pf f =1 mhz, code = full scale ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specif ied operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4018 device only, includes v wzse and v wfse . 4: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 5: this specification by design. 6: non-linearity is affected by wiper resistance (r w ), which changes signific antly over voltage and temperature. 7: por/bor is not rate dependent. 8: supply current is independent of current through the resistor network
MCP4017/18/19 ds22147a-page 8 ? 2009 microchip technology inc. digital inputs/outputs (sda, sck) schmitt trigger high input threshold v ih 0.7 v dd ?? v1.8v v dd 5.5v schmitt trigger low input threshold v il -0.5 ? 0.3v dd v hysteresis of schmitt trigger inputs (note 5) v hys ?0.1v dd ? v all inputs except sda and scl n.a. ? ? v sda and scl 100 khz v dd < 2.0v n.a. ? ? v v dd 2.0v 0.1 v dd ?? v 400 khz v dd < 2.0v 0.05 v dd ?? v v dd 2.0v output low voltage (sda) v ol v ss ?0.2v dd vv dd < 2.0v, i ol = 1 ma v ss ?0.4 vv dd 2.0v, i ol = 3 ma input leakage current i il -1 ? 1 a v in = v dd and v in = v ss pin capacitance c in , c out ?10?pff c = 400 khz ram (wiper) value value range n 0h ? 7fh hex wiper por/bor value n por/bor 3fh hex power requirements power supply sensitivity ( mcp4018 only) pss ? 0.0005 0.0035 %/% v dd = 2.7v to 5.5v, v a = 2.7v, code = 3fh ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specif ied operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4018 device only, includes v wzse and v wfse . 4: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 5: this specification by design. 6: non-linearity is affected by wiper resistance (r w ), which changes signific antly over voltage and temperature. 7: por/bor is not rate dependent. 8: supply current is independent of current through the resistor network
? 2009 microchip technology inc. ds22147a-page 9 MCP4017/18/19 1.1 i 2 c mode timing waveforms and requirements figure 1-1: i 2 c bus start/stop bits timing waveforms. table 1-1: i 2 c bus start/stop bits requirements figure 1-2: i 2 c bus data timing. i 2 c ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +125 c (extended) operating voltage v dd range is described in section 2.0 ?typical performance curves? param. no. symbol characteristic min max units conditions f scl standard mode 0 100 khz c b = 400 pf, 1.8v - 5.5v fast mode 0 400 khz c b = 400 pf, 2.7v - 5.5v d102 cb bus capacitive loading 100 khz mode ? 400 pf 400 khz mode ? 400 pf 90 t su : sta start condition 100 khz mode 4700 ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? ns 91 t hd : sta start condition 100 khz mode 4000 ? ns after this period the first clock pulse is generated hold time 400 khz mode 600 ? ns 92 t su : sto stop condition 100 khz mode 4000 ? ns setup time 400 khz mode 600 ? ns 93 t hd : sto stop condition 100 khz mode 4000 ? ns hold time 400 khz mode 600 ? ns 91 93 scl sda start condition stop condition 90 92 note 1: refer to specification d102 (cb) for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
MCP4017/18/19 ds22147a-page 10 ? 2009 microchip technology inc. table 1-2: i 2 c bus data requirements (slave mode) i 2 c ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +125 c (extended) operating voltage v dd range is described in ac/dc characteristics parame- ter no. sym characteristic min max units conditions 100 t high clock high time 100 khz mode 4000 ? ns 1.8v-5.5v 400 khz mode 600 ? ns 2.7v-5.5v 101 t low clock low time 100 khz mode 4700 ? ns 1.8v-5.5v 400 khz mode 1300 ? ns 2.7v-5.5v 102a (5) t rscl scl rise time 100 khz mode ? 1000 ns cb is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1cb 300 ns 102b (5) t rsda sda rise time 100 khz mode ? 1000 ns cb is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1cb 300 ns 103a (5) t fscl scl fall time 100 khz mode ? 300 ns cb is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1cb 40 ns 103b (5) t fsda sda fall time 100 khz mode ? 300 ns cb is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1cb (4) 300 ns 106 t hd : dat data input hold time 100 khz mode 0 ? ns 1.8v-5.5v, note 6 400 khz mode 0 ? ns 2.7v-5.5v, note 6 107 t su : dat data input setup time 100 khz mode 250 ? ns (2) 400 khz mode 100 ? ns 109 t aa output valid from clock 100 khz mode ? 3450 ns (1) 400 khz mode ? 900 ns 110 t buf bus free time 100 khz mode 4700 ? ns time the bus must be free before a new transmission can start 400 khz mode 1300 ? ns t sp input filter spike suppression (sda and scl) 100 khz mode ? 50 ns philips spec states n.a. 400 khz mode ? 50 ns note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid un intended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement tsu; dat 250 ns must then be met. th is will automatically be the ca se if the device does not stretch the low period of the scl signal. if such a dev ice does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+tsu;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus specification) before the scl line is released. 3: the mcp4018/mcp4019 device must provide a data hold time to bridge the undefined part between v ih and v il of the falling edge of the scl signal. this specification is not a part of the i 2 c specification, but must be tested in order to guarantee that the output data will meet the setup and hold specifications for the receiv- ing device. 4: use cb in pf for the calculations. 5: not tested. 6: a master transmitter must provide a delay to ensure that difference between sda and scl fall times do not unintentionally create a st art or stop condition.
? 2009 microchip technology inc. ds22147a-page 11 MCP4017/18/19 temperature characteristics electrical specifications: unless otherwise indicated, v dd = +1.8v to +5.5v, v ss =gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 5l-sc70 (note 1) ja ?331?c/w thermal resistance, 6l-sc70 ja ?tbd?c/w note 1: package power dissipation (pdis) is calculated as follows: p dis = (t j - t a ) / ja , where: t j = junction temperature, t a = ambient temperature.
MCP4017/18/19 ds22147a-page 12 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds22147a-page 13 MCP4017/18/19 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-1: interface active current (i dd ) vs. scl frequency (f scl ) and temperature (v dd = 1.8v, 2.7v and 5.5v). figure 2-2: interface inac tive current (i shdn ) vs. temperature and v dd . (v dd = 1.8v, 2.7v and 5.5v). note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purpose s only. the performance characteristics listed herein are not tested or guaranteed. in so me graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power suppl y range) and therefore outs ide the warranted range. 0 10 20 30 40 50 60 -40 0 40 80 120 temperature (c) i dd (a) 100 khz, 5.5v 400 khz, 5.5v 100 khz, 2.7v 400 khz, 2.7v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -40 0 40 80 120 temperature (c) i dd interface inactive (a) 5.5v 2.7v
MCP4017/18/19 ds22147a-page 14 ? 2009 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-3: 5.0 k : pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 5.5v). (a = v dd , b = v ss ). figure 2-4: 5.0 k : pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 2.7v). (a = v dd , b = v ss ) figure 2-5: 5.0 k : pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 1.8v). (a = v dd , b = v ss ) figure 2-6: 5.0 k : rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 5.5v).(i w = 1.4ma, b = v ss ) figure 2-7: 5.0 k : rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 2.7v).(i w = 450ua, b = v ss ) figure 2-8: 5.0 k : rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 1.8v). (i w = tbd, b = v ss ) 20 40 60 80 100 120 0 326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl -40c 25c 85 r w 125c note: refer to an1080 for additional informa- tion on the characteristics of the wiper resistance (r w ) with respect to device voltage and wiper setting value. 0 500 1000 1500 2000 2500 0 326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.35 -0.25 -0.15 -0.05 0.05 0.15 0.25 0.35 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw 20 40 60 80 100 120 0 326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -1 0 1 2 3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c note: refer to an1080 for additional informa- tion on the characteristics of the wiper resistance (r w ) with respect to device voltage and wiper setting value. 0 500 1000 1500 2000 2500 0326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -1 4 9 14 19 24 29 34 39 44 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw
? 2009 microchip technology inc. ds22147a-page 15 MCP4017/18/19 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-9: 5.0 k : full scale error (fse) vs. temperature (v dd = 5.5v, 2.7v, 1.8v). figure 2-10: 5.0 k : zero scale error (zse) vs. temperature (v dd = 5.5v, 2.7v, 1.8v). figure 2-11: 5.0 k : nominal resistance ( ) vs. temperature and v dd . figure 2-12: 5.0 k : r bw tempco r wb / t vs. code. figure 2-13: 5.0 k : power-up wiper response time. figure 2-14: 5.0 k : digital feedthrough (scl signal coupling to wiper pin). -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 -40 0 40 80 120 ambient temperature (c) full-scale error (fse) (lsb) 2.7 5.5v 1.8v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -40 0 40 80 120 ambient temperature (c) zero-scale error (zse) (lsb) 2.7 5.5v 1.8v 5000 5020 5040 5060 5080 5100 5120 5140 5160 5180 5200 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 2.7v 5.5v 1.8v 0 20 40 60 80 100 120 140 160 180 200 0 326496 wiper setting (decimal) r bw tempco (ppm) 2.7v 5.5v wiper v dd
MCP4017/18/19 ds22147a-page 16 ? 2009 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-15: 5.0 k : write wiper (40h 3fh) settling time (v dd =5.5v). figure 2-16: 5.0 k : write wiper (40h 3fh) settling time (v dd =2.7v). figure 2-17: 5.0 k : write wiper (40h 3fh) settling time (v dd =1.8v). figure 2-18: 5.0 k : write wiper (ffh 00h) settling time (v dd =5.5v). figure 2-19: 5.0 k : write wiper (ffh 00h) settling time (v dd =2.7v). figure 2-20: 5.0 k : write wiper (ffh 00h) settling time (v dd =1.8v).
? 2009 microchip technology inc. ds22147a-page 17 MCP4017/18/19 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-21: 10 k pot mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 5.5v). (a = v dd , b = v ss ) figure 2-22: 10 k pot mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 2.7v). (a = v dd , b = v ss ) figure 2-23: 10 k pot mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 1.8v). (a = v dd , b = v ss ) figure 2-24: 10 k rheo mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 5.5v).(i w = 450ua, b = v ss ) figure 2-25: 10 k rheo mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 2.7v).(i w = 210ua, b = v ss ) figure 2-26: 10 k rheo mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 1.8v). (i w = tbd, b = v ss ) 20 40 60 80 100 120 0 326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl -40c 25c 85 r w 125c note: refer to an1080 for additional informa- tion on the characteristics of the wiper resistance (r w ) with respect to device voltage and wiper setting value. 0 1000 2000 3000 0 326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.35 -0.25 -0.15 -0.05 0.05 0.15 0.25 0.35 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw 20 40 60 80 100 120 0 326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -1 0 1 2 3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c note: refer to an1080 for additional informa- tion on the characteristics of the wiper resistance (r w ) with respect to device voltage and wiper setting value. 0 1000 2000 3000 0326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -1 4 9 14 19 24 29 34 39 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw
MCP4017/18/19 ds22147a-page 18 ? 2009 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-27: 10 k : full scale error (fse) vs. temperature (v dd = 5.5v, 2.7v, 1.8v). figure 2-28: 10 k : zero scale error (zse) vs. temperature (v dd = 5.5v, 2.7v, 1.8v). figure 2-29: 10 k : nominal resistance ( ) vs. temperature and v dd . figure 2-30: 10 k : r bw tempco r wb / t vs. code. figure 2-31: 10 k : power-up wiper response time. figure 2-32: 10 k : digital feedthrough (scl signal coupling to wiper pin). -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 -40 0 40 80 120 ambient temperature (c) full-scale error (fse) (lsb) 2.7 5.5v 1.8v 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -40 0 40 80 120 ambient temperature (c) zero-scale error (zse) (lsb) 2.7 5.5v 1.8v 9900 9950 10000 10050 10100 10150 10200 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 2.7 5.5v 1.8v 0 20 40 60 80 100 0 326496 wiper setting (decimal) r bw tempco (ppm) 2.7v 5.5v wiper v dd
? 2009 microchip technology inc. ds22147a-page 19 MCP4017/18/19 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-33: 10 k : write wiper (40h 3fh) settling time (v dd =5.5v). figure 2-34: 10 k : write wiper (40h 3fh) settling time (v dd =2.7v). figure 2-35: 10 k : write wiper (40h 3fh) settling time (v dd =1.8v). figure 2-36: 10 k : write wiper (ffh 00h) settling time (v dd =5.5v). figure 2-37: 10 k : write wiper (ffh 00h) settling time (v dd =2.7v). figure 2-38: 10 k : write wiper (ffh 00h) settling time (v dd =1.8v).
MCP4017/18/19 ds22147a-page 20 ? 2009 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-39: 50 k pot mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 5.5v). figure 2-40: 50 k pot mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 2.7v). figure 2-41: 50 k pot mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 1.8v). figure 2-42: 50 k rheo mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 5.5v).(i w = 90ua, b = v ss ) figure 2-43: 50 k rheo mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 2.7v).(i w = 45ua, b = v ss ) figure 2-44: 50 k rheo mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 1.8v). (i w = tbd, b = v ss ) 20 40 60 80 100 120 0 326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl -40c 25c 85 r w 125c note: refer to an1080 for additional informa- tion on the characteristics of the wiper resistance (r w ) with respect to device voltage and wiper setting value. 0 2000 4000 6000 8000 10000 0326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.35 -0.25 -0.15 -0.05 0.05 0.15 0.25 0.35 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw 20 40 60 80 100 120 0 326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c note: refer to an1080 for additional informa- tion on the characteristics of the wiper resistance (r w ) with respect to device voltage and wiper setting value. 0 2000 4000 6000 8000 10000 0326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -1 1 3 5 7 9 11 13 15 17 19 21 23 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw
? 2009 microchip technology inc. ds22147a-page 21 MCP4017/18/19 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-45: 50 k : full scale error (fse) vs. temperature (v dd = 5.5v, 2.7v, 1.8v). figure 2-46: 50 k : zero scale error (zse) vs. temperature (v dd = 5.5v, 2.7v, 1.8v). figure 2-47: 50 k : nominal resistance ( ) vs. temperature and v dd . figure 2-48: 50 k : r bw tempco r wb / t vs. code. figure 2-49: 50 k : power-up wiper response time. figure 2-50: 50 k : digital feedthrough (scl signal coupling to wiper pin). -0.16 -0.12 -0.08 -0.04 0.00 -40 0 40 80 120 ambient temperature (c) full-scale error (fse) (lsb) 2.7 5.5v 1.8v 0.00 0.04 0.08 0.12 0.16 0.20 -40 0 40 80 120 ambient temperature (c) zero-scale error (zse) (lsb) 2.7 5.5v 1.8v 48800 49000 49200 49400 49600 49800 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 2.7v 5.5v 1.8v 0 20 40 60 80 100 0 326496 wiper setting (decimal) r bw tempco (ppm) 2.7v 5.5v wiper v dd
MCP4017/18/19 ds22147a-page 22 ? 2009 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-51: 50 k : write wiper (40h 3fh) settling time (v dd =5.5v). figure 2-52: 50 k : write wiper (40h 3fh) settling time (v dd =2.7v). figure 2-53: 50 k : write wiper (40h 3fh) settling time (v dd =1.8v). figure 2-54: 50 k : write wiper (ffh 00h) settling time (v dd =5.5v). figure 2-55: 50 k : write wiper (ffh 00h) settling time (v dd =2.7v). figure 2-56: 50 k : write wiper (ffh 00h) settling time (v dd =1.8v).
? 2009 microchip technology inc. ds22147a-page 23 MCP4017/18/19 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-57: 100 k pot mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 5.5v). figure 2-58: 100 k pot mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 2.7v). figure 2-59: 100 k pot mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 1.8v). figure 2-60: 100 k rheo mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 5.5v). (i w = 45ua, b = v ss ) figure 2-61: 100 k rheo mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 2.7v). (i w = 21ua, b = v ss ) figure 2-62: 100 k rheo mode : r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and temperature (v dd = 1.8v). (i w = tbd, b = v ss ) 20 40 60 80 100 120 0 326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl -40c 25c 85 r w 125c note: refer to an1080 for additional informa- tion on the characteristics of the wiper resistance (r w ) with respect to device voltage and wiper setting value. 0 2500 5000 7500 10000 12500 15000 0326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.35 -0.25 -0.15 -0.05 0.05 0.15 0.25 0.35 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw 20 40 60 80 100 120 0 326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c note: refer to an1080 for additional informa- tion on the characteristics of the wiper resistance (r w ) with respect to device voltage and wiper setting value. 0 2500 5000 7500 10000 12500 15000 0326496 wiper setting (decimal) wiper resistance (r w ) (ohms) -1 1 3 5 7 9 11 13 15 17 19 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw
MCP4017/18/19 ds22147a-page 24 ? 2009 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-63: 100 k : full scale error (fse) vs. temperature (v dd = 5.5v, 2.7v, 1.8v). figure 2-64: 100 k : zero scale error (zse) vs. temperature (v dd = 5.5v, 2.7v, 1.8v). figure 2-65: 100 k : nominal resistance ( ) vs. temperature and v dd . figure 2-66: 100 k : r bw tempco r wb / t vs. code. figure 2-67: 100 k : power-up wiper response time. figure 2-68: 100 k : digital feedthrough (scl signal coupling to wiper pin). -0.08 -0.06 -0.04 -0.02 0.00 -40 0 40 80 120 ambient temperature (c) full-scale error (fse) (lsb) 2.7 5.5v 1.8v 0.00 0.04 0.08 0.12 -40 0 40 80 120 ambient temperature (c) zero-scale error (zse) (lsb) 2.7 5.5v 1.8v 97800 98000 98200 98400 98600 98800 99000 99200 99400 99600 99800 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 2.7v 5.5v 1.8v 0 20 40 60 80 100 0 326496 wiper setting (decimal) r bw tempco (ppm) 2.7v 5.5v wiper v dd
? 2009 microchip technology inc. ds22147a-page 25 MCP4017/18/19 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-69: 100 k : write wiper (40h 3fh) settling time (v dd = 5.5v). figure 2-70: 100 k : write wiper (40h 3fh) settling time (v dd = 2.7v). figure 2-71: 100 k : write wiper (40h 3fh) settling time (v dd = 1.8v). figure 2-72: 100 k : write wiper (ffh 00h) settling time (v dd = 5.5v). figure 2-73: 100 k : write wiper (ffh 00h) settling time (v dd = 2.7v). figure 2-74: 100 k : write wiper (ffh 00h) settling time (v dd = 1.8v).
MCP4017/18/19 ds22147a-page 26 ? 2009 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-75: v ih (scl, sda) vs. v dd and temperature. figure 2-76: v il (scl, sda) vs. v dd and temperature. figure 2-77: v ol (sda) vs. v dd and temperature. figure 2-78: por/bor trip point vs. v dd and temperature. 0 0.5 1 1.5 2 2.5 3 3.5 4 -40 0 40 80 120 temperature (c) v ih (v) 5.5v 2.7v 1.8v 0 0.5 1 1.5 2 -40 0 40 80 120 temperature (c) v il (v) 5.5v 2.7v 1.8v 0 0.05 0.1 0.15 0.2 0.25 0.3 -40 0 40 80 120 temperature (c) v ol (mv) 5.5v (@ 3ma) 2.7v (@ 3ma) 1.8v (@ 1ma) 0 0.2 0.4 0.6 0.8 1 1.2 -40 0 40 80 120 temperature (c) v dd (v) 5.5 v 2.7v
? 2009 microchip technology inc. ds22147a-page 27 MCP4017/18/19 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-79: 5k ? gain vs. frequency (-3db). figure 2-80: 10 k ? gain vs. frequency (-3db). figure 2-81: 50 k ? gain vs. frequency (-3db). figure 2-82: 100 k ? gain vs. frequency (-3db). 2.1 test circuits figure 2-83: gain vs. frequency test (-3db). -50 -40 -30 -20 -10 0 10 100 1,000 10,000 frequency (khz) db code = 7fh code = 3fh code = 01h code = 0fh code = 1fh -60 -50 -40 -30 -20 -10 0 10 100 1,000 10,000 frequency (khz) db code = 7fh code = 3fh code = 01h code = 0fh code = 1fh -60 -50 -40 -30 -20 -10 0 10 100 1,000 10,000 frequency (khz) db code = 7fh code = 3fh code = 0fh code = 1fh code = 01h -60 -50 -40 -30 -20 -10 0 10 100 1,000 10,000 frequency (khz) db code = 7fh code = 3fh code = 0fh code = 1fh code = 01h + - v out +5v a b w v in +5v
MCP4017/18/19 ds22147a-page 28 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds22147a-page 29 MCP4017/18/19 3.0 pin descriptions the descriptions of the pins are listed in ta b l e 3 - 1 . additional descriptions of the device pins follow. table 3-1: pinout descript ion for the MCP4017/18/19 pin name pin number pin type buffer type function MCP4017 (sc70-6) mcp4018 (sc70-6) mcp4019 (sc70-5) v dd 1 1 1 p ? positive power supply input v ss 2 2 2 p ? ground scl333i/ost (od)i 2 c serial clock pin sda444i/ost (od)i 2 c serial data pin b 5 ? ? i/o a potentiometer terminal b w 6 5 5 i/o a potentiometer wiper terminal a ? 6 ? i/o a potentiometer terminal a legend: a = analog input st (od) = schmitt trigger with open drain i = input o = output i/ o = input/output p = power
MCP4017/18/19 ds22147a-page 30 ? 2009 microchip technology inc. 3.1 positive power supply input (v dd ) the v dd pin is the device?s positive power supply input. the input power supply is relative to v ss and can range from 1.8v to 5.5v. a de-coupling capacitor on v dd (to v ss ) is recommended to achieve maximum performance. while the device?s voltage is in the range of 1.8v v dd < 2.7v, the resistor network?s electrical performance of the device may not meet the data sheet specifications. 3.2 ground (v ss ) the v ss pin is the device ground reference. 3.3 i 2 c serial clock (scl) the scl pin is the serial clock pin of the i 2 c interface. the mcp401x acts only as a slave and the scl pin accepts only external serial clocks. the scl pin is an open-drain output. refer to section 5.0 ?serial interface - i 2 c module? for more details of i 2 c serial interface communication. 3.4 i 2 c serial data (sda) the sda pin is the serial data pin of the i 2 c interface. the sda pin has a schmitt trigger input and an open-drain output. refer to section 5.0 ?serial interface - i 2 c module? for more details of i 2 c serial interface communication. 3.5 potentiometer terminal b the terminal b pin (available on some devices) is connected to the internal potentiometer?s terminal b. the potentiometer?s terminal b is the fixed connection to the zero scale (0x00 tap) wiper value of the digital potentiometer. the terminal b pin is available on the MCP4017 device. the terminal b pin does not have a polarity relative to the terminal w pin. the terminal b pin can support both positive and negative current. the voltage on terminal b must be between v ss and v dd . the terminal b pin is not available on the mcp4018 and mcp4019 devices. for these devices, the potentiometer?s terminal b is internally connected to v ss . 3.6 potentiometer wiper (w) terminal the terminal w pin is connected to the internal potentiometer?s terminal w (the wiper). the wiper terminal is the adjustable terminal of the digital potentiometer. the terminal w pin does not have a polarity relative to terminals a or b pins. the terminal w pin can support both positive and negative current. the voltage on terminal w must be between v ss and v dd . 3.7 potentiometer terminal a the terminal a pin (available on some devices) is connected to the internal potentiometer?s terminal a. the potentiometer?s terminal a is the fixed connection to the full scale (0x7f tap) wiper value of the digital potentiometer. the terminal a pin is available on the mcp4018 devices. the terminal a pin does not have a polarity relative to the terminal w pin. the terminal a pin can support both positive and negative current. the voltage on terminal a must be between v ss and v dd . the terminal a pin is not available on the MCP4017 and mcp4019 devices. for these devices, the potentiometer?s terminal a is internally floating.
? 2009 microchip technology inc. ds22147a-page 31 MCP4017/18/19 4.0 general overview the MCP4017/18/19 devices are general purpose digital potentiometers intended to be used in applications where a programmable resistance with moderate bandwidth is desired. this data sheet covers a family of three digital potentiometer and rheostat devices. the mcp4018 device is the potentiometer configuration, while the MCP4017 and mcp4019 devices are the rheostat configuration. applications generally suited for the mcp401x devices include: ? set point or offset trimming ? sensor calibration ? selectable gain and offset amplifier designs ? cost-sensitive mechanical trim pot replacement as the device block diagram shows, there are four main functional blocks. these are: ? por/bor operation ? serial interface - i 2 c module ? resistor network the por/bor operation an d the memory map are discussed in this section and the i 2 c and resistor network operation are described in their own sections. the serial commands commands are discussed in section 5.4 . 4.1 por/bor operation the power-on reset is the case where the device is having power applied to it from v ss . the brown-out reset occurs when a device had power applied to it, and that power (voltage) drops below the specified range. the devices ram retention voltage (v ram ) is lower than the por/bor voltage trip point (v por /v bor ). the maximum v por /v bor voltage is less then 1.8v. when v por /v bor < v dd < 2.7v, the resistor network?s electrical performance may not meet the data sheet specifications. in this region, the device is capable of reading and writing to its vo latile memory if the proper serial command is executed. table 4-1 shows the digital pot?s level of functionality across the entire v dd range, while figure 4-1 illustrates the power-up and brown-out functionality. 4.1.1 power-on reset when the device powers up, the device v dd will cross the v por /v bor voltage. once the v dd voltage crosses the v por /v bor voltage, the following happens: ? volatile wiper register is loaded with the default wiper value (3fh) ? the device is capable of digital operation 4.1.2 brown-out reset when the device powers down, the device v dd will cross the v por /v bor voltage. once the v dd voltage decreases below the v por /v bor voltage the following happens: ? serial interface is disabled if the v dd voltage decreases below the v ram voltage the following happens: ? volatile wiper registers may become corrupted as the voltage recovers above the v por /v bor voltage see section 4.1.1 ?power-on reset? . serial commands not completed due to a brown-out condition may cause the memory location to become corrupted. 4.1.3 wiper register (ram) the wiper register is volatile memory that starts functioning at the ra m retention voltage (v ram ). the wiper register will be lo aded with the default wiper value when v dd will rise above the v por /v bor voltage. 4.1.4 device currents the current of the device can be classified into two modes of the device operation. these are: ? serial interface inactive (static operation) ? serial interface active static operation occurs when a stop condition is received. static operation is exited when a start condition is received.
MCP4017/18/19 ds22147a-page 32 ? 2009 microchip technology inc. table 4-1: device functionality at each v dd region (note 1) figure 4-1: power-up and brown-out. v dd level serial interface potentiometer terminals wiper setting comment v dd < v bor < 1.8v ignored ?unknown? unknown v bor v dd < 1.8v ?unknown? operational with reduced electrical specs wiper register loaded with por/bor value 1.8v v dd < 2.7v accepted operational with reduced electrical specs wiper register determines wiper setting electrical performance may not meet the data sheet specifications. 2.7v v dd 5.5v accepted operational wiper register determines wiper setting meets the data sheet specifications note 1: for system voltages below the minimum operating voltage, the customer will be recommended to use a voltage supervisor to hold the system in reset. this will ensure that mcp 4017/18/19 commands are not attempted out of the operating range of the device. v por/bor v ss v dd 2.7v outside specified normal operation range device?s serial wiper forced to default por/bor setting v bor delay normal operation range 1.8v interface is ?not operational? ac/dc range analog characteristics not specified analog characteristics not specified v ram
? 2009 microchip technology inc. ds22147a-page 33 MCP4017/18/19 5.0 serial interface - i 2 c module a 2-wire i 2 c serial protocol is used to write or read the digital potentiometer?s wiper register. the i 2 c protocol utilizes the scl input pin and sda input/output pin. the i 2 c serial interface supports the following features. ? slave mode of operation ? 7-bit addressing ? the following clock rate modes are supported: - standard mode, bit rates up to 100 kb/s - fast mode, bit rates up to 400 kb/s ? support multi-master applications the serial clock is generated by the master. the i 2 c module is compatible with the phillips i 2 c specification. phillips only defines the field types, field lengths, timings, etc. of a frame. the frame content defines the behavior of th e device. the frame content for the MCP4017, mcp4018, and mcp4019 devices are defined in this section of the data sheet. figure 5-1 shows a typical i 2 c bus configurations. figure 5-1: typical application i 2 c bus configurations. refer to section 2.0 ?typical performance curves? , ac/dc electrical characteristics table for detailed input threshold and timing specifications. 5.1 i 2 c i/o considerations i 2 c specifications require active low, passive high functionality on devices interfacing to the bus. since devices may be operating on separate power supply sources, esd clamping diod es are not permitted. the specification recommends using open drain transistors tied to v ss (common) with a pull-up resistor. the specification makes some general recommendations on the size of this pull-up , but does not specify the exact value since bus speeds and bus capacitance impacts the pull-up value for optimum system performance. common pull-up values range from 1 k to a max of ~10 k . power sensitive applications tend to choose higher values to minimize current losses during communication but these applications also typically utilize lower v dd . the sda and scl float (are not driving) when the device is powered down. a "glitch" filter is on the scl and sda pins when the pin is an input. when these pins are an output, there is a slew rate control of the pin that is independent of device frequency. 5.1.1 slope control the device implements slope control on the sda output. the slope control is defined by the fast mode specifications. for fast (fs) mode, the device has spike suppression and schmidt trigger inputs on the sda and scl pins. single i 2 c bus configuration host controller device 1 device 3 device n device 2 device 4
MCP4017/18/19 ds22147a-page 34 ? 2009 microchip technology inc. 5.2 i 2 c bit definitions i 2 c bit definitions include: ? start bit ? data bit ? acknowledge (a) bit ? repeated start bit ? stop bit ? clock stretching figure 5-8 shows the waveform for these states. 5.2.1 start bit the start bit (see figure 5-2 ) indicates the beginning of a data transfer sequence. the start bit is defined as the sda signal falling when the scl signal is ?high?. figure 5-2: start bit. 5.2.2 data bit the sda signal may change state while the scl signal is low. while the scl signal is high, the sda signal must be stable (see figure 5-3 ). figure 5-3: data bit. 5.2.3 acknowledge (a) bit the a bit (see figure 5-4 ) is a response from the slave device to the master device. depending on the context of the transfer sequence, the a bit may indicate different things. typically the slave device will supply an a response after the start bit and 8 ?data? bits have been received. the a bit will have the sda signal low. figure 5-4: acknowledge waveform. if the slave address is not valid, the slave device will issue a not a (a ). the a bit will have the sda signal high. if an error condition occurs (such as an a instead of a) then an start bit must be issued to reset the command state machine. table 5-1: MCP4017/18/19 a / a responses 5.2.4 repeated start bit the repeated start bit (see figure 5-5 ) indicates the current master device wishes to continue communicating with the current slave device without releasing the i 2 c bus. the repeated start condition is the same as the start condition, except that the repeated start bit follows a start bit (with the data bits + a bit) and not a stop bit. the start bit is the beginning of a data transfer sequence and is defined as the sda signal falling when the scl signal is ?high?. figure 5-5: repeat start condition waveform. sda scl s 1st bit 2nd bit sda scl s 1st bit 2nd bit a 8 d0 9 sda scl event acknowledge bit response comment general call a slave address valid a slave address not valid a bus collision n.a. i 2 c module resets, or a ?don?t care? if the collision occurs on the masters ?start bit?. note 1: a bus collision during the repeated start condition occurs if: ? sda is sampled low when scl goes from low to high. ? scl goes low before sda is asserted low. this may indica te that another mas- ter is attempting to transmit a data "1". sda scl sr = repeated start 1st bit
? 2009 microchip technology inc. ds22147a-page 35 MCP4017/18/19 5.2.5 stop bit the stop bit (see figure 5-6 ) indicates the end of the i 2 c data transfer sequence. the stop bit is defined as the sda signal rising when the scl signal is ?high?. a stop bit resets the i 2 c interface of the other devices. figure 5-6: stop condition receive or transmit mode. 5.2.6 clock stretching ?clock stretching? is something that the secondary device can do, to allow additional time to ?respond? to the ?data? that has been received. the MCP4017/18/19 will not strech the clock signal (scl) since memory read accesses occur fast enough. 5.2.7 aborting a transmission if any part of the i 2 c transmission does not meet the command format, it is abort ed. this can be intentionally accomplished with a start or stop condition. this is done so that noisy transmissions (usually an extra start or stop condition) are aborted before they corrupt the device. 5.2.8 ignoring an i 2 c transmission and ?falling off? the bus the MCP4017/18/19 expects to receive entire, valid i 2 c commands and will assume any command not defined as a valid command is due to a bus corruption and will enter a passive high condition on the sda signal. all signals will be ignored until the next valid start condition and control byte are received. figure 5-7: typical 16-bit i 2 c waveform format. figure 5-8: i 2 c data states and bit sequence. scl sda a / a p 1st sda scl s 2nd 3rd 4th 5th 6th 7th 8th p a/a bit bit bit bit bit bit bit bit 1st 2nd 3rd 4th 5t h 6th 7th 8th a/a bit bit bit bit bit bit bit bit scl sda start condition stop condition data allowed to change data or a valid
MCP4017/18/19 ds22147a-page 36 ? 2009 microchip technology inc. 5.2.9 i 2 c command protocol the MCP4017/18/19 is a slave i 2 c device which supports 7-bit slave addressing. the slave address contains seven fixed bits. figure 5-9 shows the control byte format. 5.2.9.1 control byte (slave address) the control byte is always preceded by a start condition. the control byte contains the slave address consisting of seven fixed bits and the r/w bit. figure 5- 9 shows the control byte format and table 5-2 shows the i 2 c address for the devices. figure 5-9: slave address bits in the i 2 c control byte. table 5-2: device i 2 c address 5.2.9.2 hardware address pins the MCP4017/mcp4018/mcp4019 does not support hardware address bits. 5.2.10 general call the general call is a method that the master device can communicate with all other slave devices. the MCP4017/18/19 devices do not respond to general call address and commands, and therefore the communications are not acknowledged. figure 5-10: general call formats. sa6a5a4a3a2a1a0r/w a/a start bit slave address r/w bit a bit (controlled by slave device) r/w = 0 = write r/w = 1 = read a = 0 = slave device acknowledges byte a = 1 = slave device does not acknowledge byte ?0? ?1? ?0? ?1? ?1? ?1? ?1? device i 2 c address comment MCP4017 ? 0101111 ? mcp4018 ? 0101111 ? mcp4019 ? 0101111 ? 0 000 s 0000 x xxxx axx0ap general call address second byte ?7-bit command? reserved 7-bit commands (by i 2 c specification - philips # 9398 393 40011, ver. 2.1 january 2000) ?0000 011?b - reset and write programmable part of slave address by hardware. ?0000 010?b - write programmable part of slave address by hardware. ?0000 000?b - not allowed the following is a ?hardware general call? format 0 000 s 0000 x xxxx a xx1a general call address second byte ?7-bit command? x xxxx xxxap n occurrences of (data + a / a) this indicates a ?hardware general call? mcp4016/7/8/9 will ignore this byte and all following bytes (and a), until a stop bit (p) is encountered.
? 2009 microchip technology inc. ds22147a-page 37 MCP4017/18/19 5.3 software reset sequence at times it may become necessary to perform a software reset sequence to ensure the MCP4017/18/ 19 device is in a correct and known i 2 c interface state. this only resets the i 2 c state machine. this is useful if the mc p4017/18/19 device powers up in an incorrect state (due to excessive bus noise, etc), or if the master device is reset during communication. figure 5-11 shows the communication sequence to software reset the device. figure 5-11: software reset sequence format. the 1st start bit will cause the device to reset from a state in which it is expecting to receive data from the master device.in this mode , the device is monitoring the data bus in receive mode and can detect the start bit forces an internal reset. the nine bits of ? 1 ? are used to force a reset of those devices that could not be reset by the previous start bit. this occurs only if the mc p4017/18/19 is driving an a on the i 2 c bus, or is in output mode (from a read command) and is driving a data bit of ? 0 ? onto the i 2 c bus. in both of these cases, the previous start bit could not be generated due to the MCP4017/18/19 holding the bus low. by sending out nine ? 1 ? bits, it is ensured that the device will see a a (the master device does not drive the i 2 c bus low to acknowledge the data sent by the MCP4017/18/19), which also forces the MCP4017/ 18/19 to reset. the 2nd start bit is sent to address the rare possibility of an erroneous write. this could occur if the master device was reset while se nding a write command to the MCP4017/18/19, and then as the master device returns to normal operation and issues a start condition while the MCP4017/18/19 is issuing an a. in this case if the 2nd start bit is not sent (and the stop bit was sent) the MCP4017/18/19 could initiate a write cycle. the stop bit terminates the current i 2 c bus activity. the MCP4017/18/19 wait to detect the next start condition. this sequence does not effect any other i 2 c devices which may be on the bus, as they should disregard this as an invalid command. 5.4 serial commands the MCP4017/18/19 devices support 2 serial commands. these commands are: ? write operation ? read operations note: this technique should be supported by any i 2 c compliant device. the 24xxxx i 2 c serial eeprom devices support this tech- nique, which is documented in an1028. note: the potential for this erroneous write only occurs if the master device is reset while sending a write command to the MCP4017/18/19. s ?1? ?1? ?1? ?1? ?1? ?1? ?1? ?1? s p start bit nine bits of ?1? start bit stop bit
MCP4017/18/19 ds22147a-page 38 ? 2009 microchip technology inc. 5.4.1 write operation the write operation requires the start condition, control byte, acknowledge, data byte, acknowledge and stop (or restart) condition. the control (slave address) byte requires the r/w bit equal to a logic zero (r/w = ?0?) to generate a write sequence. the MCP4017/18/19 is responsible for generating the acknowledge (a) bits. data is written to the MCP4017/18/19 after every byte transfer (during the a bit). if a stop or restart condition is generated during a data transfer (before the a bit), the data will not be written to MCP4017/18/ 19. data bytes may be written after each acknowledge. the command is terminated once a stop (p) condition occurs. refer to figure 5-12 for the write sequence. for a single byte write, the master sends a stop or restart condition after the 1st data byte is sent. the msb of each data byte is a don?t care, since the wiper register is only 7-bits wide. figure 5-14 shows the i 2 c communication behavior of the master device and the MCP4017/18/19 device and the resultant i 2 c bus values. 5.4.2 read operations the read operation requires the start condition, control byte, acknowledge, data byte, the master generating the a and stop condition. the control byte requires the r/w bit equal to a logic one (r/w = 1) to generate a read sequence. the MCP4017/18/19 will a the slave address byte and a all the data bytes. the i 2 c master will a the slave address byte and the last data byte. if there are multiple data bytes, the i 2 c master will a all data bytes except the last data byte (which it will a ). the MCP4017/18/19 maintains control of the sda signal until all data bits have been clocked out. the command is terminated once a stop (p) condition occurs. refer to figure 5-13 for the read command sequence. for a single read, the master sends a stop or restart condition after the 1st data byte (and a bit) is sent from the slave. figure 5-14 shows the i 2 c communication behavior of the master device and the MCP4017/18/19 device and the resultant i 2 c bus values. figure 5-12: i 2 c write command format. stop bit slave address byte data byte data byte 1 010 s1110 d3 ad2d1d0ad3 xd6d5d4 d2d1d0a fixed address data byte data byte ad3 x d6d5d4 d2d1d0 a p read/write bit (?0? = write) xd6d5d4 d3 d2 d1 d0 xd6d5d4 s = start condition p = stop condition a = acknowledge x = don?t care r/w = read/write bit d6, d5, d4, d3, d2, d1, d0 = data bits legend
? 2009 microchip technology inc. ds22147a-page 39 MCP4017/18/19 figure 5-13: i 2 c read command format. stop bit slave address byte data byte data byte 1 010 s1111 d3 ad2d1d0a(1)d3 0d6d5d4 d2d1d0a(1) fixed address data byte data byte a(1) d3 0 d6d5d4 d2d1d0a (2) p read/write bit (?1? = read) 0d6d5d4 d3 d2 d1 d0 0d6d5d4 s = start condition p = stop condition a = acknowledge x = don?t care r/ w = read/write bit note 1 = data bits legend note 1: master device is responsible for a / a si gnal. if a a signal occurs, the MCP4017/18/19 will abort this transfer and release the bus. 2: the master device will a, and t he MCP4017/18/19 will release the bus so the master device can generate a stop or rep eated start condition.
MCP4017/18/19 ds22147a-page 40 ? 2009 microchip technology inc. figure 5-14: i 2 c communication behavior. write 1 byte write 2 bytes read 1 byte read 2 bytes s slave address r / w a data byte (1) ap master s010111101xddddddd1p MCP4017/18/19 0 0 i 2 c bus s010111100xddddddd0p s slave address r / w a data byte (1) adata byte (1) ap master s010111101xddddddd1xddddddd1p MCP4017/18/19 0 0 0 i 2 c bus s010111100xddddddd0xddddddd1p s slave address r / wa data byte a p master s010111111 1p MCP4017/18/19 0 0 d d d d d d d 1 i 2 c bus s0101111100ddddddd1p s slave address r / w a data byte a data byte a p master s 010111111 0 1 p MCP4017/18/19 00 ddddddd 1 0ddddddd 1 i 2 c bus s 0101111100 ddddddd 00 ddddddd 1 p note 1: for write commands, the msb of the data byte is a don? t care since the wiper register is only 7-bits wide.
? 2009 microchip technology inc. ds22147a-page 41 MCP4017/18/19 6.0 resistor network the resistor network is made up of two parts. these are: ? resistor ladder ?wiper figure 6-1 shows a block diagram for the resistive network. digital potentiometer applications can be divided into two resistor network categories: ? rheostat configuration ? potentiometer (or voltage divider) configuration the MCP4017 is a true rheostat, with terminal b and the wiper (w) of the variable resistor available on pins. the mcp4018 device offers a voltage divider (potentiometer) with terminal b internally connected to ground. the mcp4019 device is a rheostat device with terminal a of the resistor floating, terminal b internally connected to ground, and the wiper (w) available on pin. 6.1 resistor ladder module the resistor ladder is a series of equal value resistors (r s ) with a connection point (tap) between the two resistors. the total number of resistors in the series (ladder) determines the r ab resistance (see figure 6- 1 ). the end points of the re sistor ladder are connected to the device terminal a and terminal b pins. the r ab (and r s ) resistance has small variations over voltage and temperature. the resistor network has 127 resistors in a string between terminal a and terminal b. this gives 7-bits of resolution. the wiper can be set to tap onto any of these 127 resistors thus providing 128 possible settings (including terminal a and terminal b). this allows zero scale to full scale connections. a wiper setting of 00h connects the terminal w (wiper) to terminal b (zero scale). a wiper setting of 3fh is the mid scale setting. a wiper setting of 7fh connects the terminal w (wiper) to terminal a (full scale). ta b l e 6 - 1 illustrates the full wiper setting map. terminal a and b as well as the wiper w do not have a polarity. these terminals can support both positive and negative current. figure 6-1: resistor network block diagram. table 6-1: wiper setting map wiper setting properties 07fh full scale (w = a) 07eh - 040h w = n 03fh w = n (mid scale) 03eh - 001h w = n 000h zero scale (w = b) r s a r s r s r s b n = 127 n = 126 n = 125 n = 1 n = 0 rw (1) w 01h analog mux rw (1) 00h rw (1) 7dh rw (1) 7eh rw (1) 7fh note 1: the wiper resistance is tap dependent. that is, each tap selection resistance has a small variation. this variation has more effect on devices with smaller r ab resistance (5.0 k ).
MCP4017/18/19 ds22147a-page 42 ? 2009 microchip technology inc. step resistance (r s ) is the resistance from one tap setting to the next. this value will be dependent on the r ab value that has been selected. equation 6-1 shows the calculation for the step resistance while table 6-2 shows the typical step resistances for each device. equation 6-1: r s calculation equation 6-2 illustrates the calculation used to determine the resistance between the wiper and terminal b. equation 6-2: r wb calculation the digital potentiometer is available in four nominal resistances (r ab ) where the nominal resistance is defined as the resistance between terminal a and terminal b. the four nominal resistances are 5 k , 10 k , 50 k , and 100 k . the total resistance of the device has minimal variation due to operating voltage (see figure 2-11 , figure 2-29 , figure 2-47 , or figure 2-65 ). table 6-2: step resistances a por/bor event will load the volatile wiper register value with the default value. table 6-3 shows the default values offered. table 6-3: default factory settings selection part number resistance ( ) case total (r ab ) step (r s ) MCP4017/18/19-502e min. 4000 31.496 typical 5000 39.370 max. 6000 47.244 MCP4017/18/19-103e min. 8000 62.992 typical 10000 78.740 max. 12000 94.488 MCP4017/18/19-503e min. 40000 314.961 typical 50000 393.701 max. 60000 472.441 MCP4017/18/19-104e min. 80000 629.921 typical 100000 787.402 max. 120000 944.882 r s r ab 127 --------- = r wb r ab n 127 ------------- - r w + = n = 0 to 127 (decimal) resistance code typical r ab value default por wiper setting code (1) -502 5.0 k mid-scale 3fh -103 10.0 k mid-scale 3fh -503 50.0 k mid-scale 3fh -104 100.0 k mid-scale 3fh note 1: custom por/bor wiper setting options are available, contact the local microchip sales office for additional information. custom options have minimum volume requirements.
? 2009 microchip technology inc. ds22147a-page 43 MCP4017/18/19 6.2 resistor configurations 6.2.1 rheostat configuration when used as a rheostat, two of the three digital potentiometer?s terminals are used as a resistive element in the circuit. with terminal w (wiper) and either terminal a or terminal b, a variable resistor is created. the resistance will depend on the tap setting of the wiper (and the wiper?s resistance). the resistance is controlled by changing the wiper setting the unused terminal (b or a) should be left floating. figure 6-2 shows the two possible resistors that can be used. reversing the polarity of the a and b terminals will not affect operation. figure 6-2: rheostat configuration. this allows the control of the total resistance between the two nodes. the total resistance depends on the ?starting? terminal to the wiper terminal. so at the code 00h, the r bw resistance is minimal (r w ), but the r aw resistance in maximized (r ab + r w ). conversely, at the code 3fh, the r aw resistance is minimal (r w ), but the r bw resistance in maximized (r ab + r w ). the resistance step size (r s ) equates to one lsb of the resistor. the pinout for the rheostat devices is such that as the wiper register is incremen ted, the resistance of the resistor will increase (as measured from terminal b to the w terminal). 6.2.2 potentiometer configuration when used as a potentiometer, all three terminals of the device are tied to different nodes in the circuit. this allows the potentiometer to output a voltage proportional to the input voltage. this configuration is sometimes called voltage divider mode. the potentiometer is used to provide a variable voltage by adjusting the wiper position between the two endpoints as shown in figure 6-3 . reversing the polarity of the a and b terminals will not affect operation. figure 6-3: potentiometer configuration. the temperature coefficient of the r ab resistors is minimal by design. in this c onfiguration, the resistors all change uniformly, so minimal variation should be seen. the wiper resistor temperature coefficient is different to the r ab temperature coefficient. the voltage at node v3 ( figure 6-3 ) is not dependent on this wiper resistance, just the ratio of the r ab resistors, so this temperature coefficient in most cases can be ignored. note: to avoid damage to the internal wiper circuitry in this configuration, care should be taken to insure t he current flow never exceeds 2.5 ma. a b w resistor r aw r bw or note: to avoid damage to the internal wiper circuitry in this configuration, care should be taken to insure t he current flow never exceeds 2.5 ma. a b w v 1 v 3 v 2
MCP4017/18/19 ds22147a-page 44 ? 2009 microchip technology inc. 6.3 wiper resistance wiper resistance is the seri es resistance of the analog switch that connects the selected resistor ladder node to the wiper terminal common signal (see figure 6-1 ). a value in the volatile wiper register selects which analog switch to close, connecting the w terminal to the selected node of the resistor ladder. the resistance is dependent on the voltages on the analog switch source, gate, and drain nodes, as well as the device?s wiper code, temperature, and the current through the switch. as the device voltage decreases, the wiper resistance increases (see figure 6-4 and table 6-4 ). the wiper can connect directly to terminal b or to terminal a. a zero scale connections, connects the terminal w (wiper) to terminal b (wiper setting of 000h). a full scale connections, connects the terminal w (wiper) to terminal a (wiper setting of 7fh). in these configurations the only resistance between the terminal w and the other terminal (a or b) is that of the analog switches. the wiper resistance is typically measured when the wiper is positioned at either zero scale (00h) or full scale (3fh). the wiper resistance in potentiometer-generated voltage divider applications is not a significant source of error. the wiper resistance in rheostat applications can create significant nonlinearity as the wiper is moved toward zero scale (00h). the lower the nominal resistance, the greater the possible error. in a rheostat configuration, this change in voltage needs to be taken into account. particularly for the lower resistance devices. for the 5.0 k device the maximum wiper resistance at 5.5v is approximately 3.2% of the total resistance, while at 2.7v it is approximately 6.5% of the total resistance. in a potentiometer configuration, the wiper resistance variation does not effect the output voltage seen on the w pin. the slope of the resistance has a linear area (at the higher voltages) and a non-linear area (at the lower voltages). in where resistance increases faster then the voltage drop (at low voltages). figure 6-4: relationship of wiper resistance (r w ) to voltage. since there is minimal variation of the total device resistance over voltage, at a constant temperature (see figure 2-11 , figure 2-29 , figure 2-47 , or figure 2-65 ), the change in wiper resistance over voltage can have a significant impact on the inl and dnl error. table 6-4: typical step resistances and relationship to wiper resistance r w v dd note: the slope of the resistance has a linear area (at the higher voltages) and a non-linear area (at the lower voltages). resistance ( )r w / r s (%) (1) r w / r ab (%) (2) typical wiper (r w ) r w = typical r w = max @ 5.5v r w = max @ 2.7v r w = typical r w = max @ 5.5v r w = max @ 2.7v total (r ab ) step (r s ) typical max @ 5.5v max @ 2.7v 5000 39.37 100 170 325 254.00% 4 31.80% 825.5% 2.00% 3.40% 6.50% 10000 78.74 100 170 325 127.00% 2 15.90% 412.75% 1. 00% 1.70% 3.25% 50000 393.70 100 170 325 25.40% 43.18% 82.55% 0.20% 0.34% 0.65% 100000 787.40 100 170 325 12.70% 21. 59% 41.28% 0.10% 0.17% 0.325% note 1: r s is the typical value. the variation of this resistance is minimal over voltage. 2: r ab is the typical value. the variation of this resistance is minimal over voltage.
? 2009 microchip technology inc. ds22147a-page 45 MCP4017/18/19 6.4 operational characteristics understanding the operational characteristics of the device?s resistor components is important to the system design. 6.4.1 accuracy 6.4.1.1 integral no n-linearity (inl) inl error for these devices is the maximum deviation between an actual code transition point and its corresponding ideal transition point after offset and gain errors have been removed. these endpoints are from 0x00 to 0x7f. refer to figure 6-5 . positive inl means higher resistance than ideal. negative inl means lower resistance than ideal. figure 6-5: inl accuracy. 6.4.1.2 differential non-linearity (dnl) dnl error is the measure of variations in code widths from the ideal code width. a dnl error of zero would imply that every code is exactly 1 lsb wide. figure 6-6: dnl accuracy. 6.4.1.3 ratiometric temperature coefficient the ratiometric temperature coefficient quantifies the error in the ratio r aw /r wb due to temperature drift. this is typically the critical error when using a potentiometer device (mcp4018) in a voltage divider configuration. 6.4.1.4 absolute temperature coefficient the absolute temperature co efficient quantifies the error in the end-to-end resistance (nominal resistance r ab ) due to temperature drift. this is typically the critical error when using a rheostat device (MCP4017 and mcp4019) in an adjustabl e resistor configuration. 111 110 101 100 011 010 001 000 digital input code actual transfer function inl < 0 ideal transfer function inl < 0 digital pot output 111 110 101 100 011 010 001 000 digital input code actual transfer function ideal transfer function narrow code < 1 lsb wide code, > 1 lsb digital pot output
MCP4017/18/19 ds22147a-page 46 ? 2009 microchip technology inc. 6.4.2 monotonic operation monotonic operation means that the device?s resistance increases with every step change (from terminal a to terminal b or terminal b to terminal a). the wiper resistances difference at each tap location. when changing from one tap position to the next (either increasing or decreasing), the r w is less then the r s . when this change occurs , the device voltage and temperature are ?the same? for the two tap positions. figure 6-7: r bw . 0x3f 0x3e 0x3d 0x03 0x02 0x01 0x00 digital input code resistance (r bw ) r w (@ tap) r s0 r s1 r s3 r s62 r s63 r bw = r sn + r w(@ tap n) n = 0 n = ?
? 2009 microchip technology inc. ds22147a-page 47 MCP4017/18/19 7.0 design considerations in the design of a system with the MCP4017/18/19 devices, the following considerations should be taken into account. these are: ? the power supply ? the layout in the design of a system with the MCP4017/18/19 devices, the following considerations should be taken into account: ? power supply considerations ? layout considerations 7.1 power supply considerations the typical application will require a bypass capacitor in order to filter high-fr equency noise, which can be induced onto the power supply's traces. the bypass capacitor helps to minimize the effect of these noise sources on signal integrity. figure 7-1 illustrates an appropriate bypass strategy. in this example, the recommended bypass capacitor value is 0.1 f. this capacitor should be placed as close to the device power pin (v dd ) as possible (within 4mm). the power source supplying these devices should be as clean as possible. if the application circuit has separate digital and analog power supplies, v dd and v ss should reside on the analog plane. figure 7-1: typical microcontroller connections. 7.2 layout considerations inductively-coupled ac transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP4017/18/19?s performance. careful board layout will minimize these effects and increase the signal-to-noise ratio (snr). bench testing has shown that a multi-layer board utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. particularly harsh environments may require shielding of critical signals. if low noise is desired, breadboards and wire-wrapped boards are not recommended. 7.2.1 resistor tempco characterization curves of the resistor temperature coefficient (tempco) are shown in figure 2-11 , figure 2-29 , figure 2-47 , and figure 2-65 . these curves show that the resistor network is designed to correct for the change in resistance as temperature increases. this technique reduces the end to end change is r ab resistance. v dd v dd v ss v ss MCP4017/18/19 0.1 f picmicro ? microcontroller 0.1 f scl sda w b a
MCP4017/18/19 ds22147a-page 48 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds22147a-page 49 MCP4017/18/19 8.0 applications examples digital potentiometers have a multitude of practical uses in modern electronic circuits. the most popular uses include precision calibration of set point thresholds, sensor trimming, lcd bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming. the MCP4017/18/19 devices can be used to replace the common mechanical trim pot in applications where the operating and terminal voltages are within cmos process limitations (v dd = 2.7v to 5.5v). 8.1 set point threshold trimming applications that need accu rate detection of an input threshold event often need several sources of error eliminated. use of comp arators and operational amplifiers (op amps) with low offset and gain error can help achieve the desired accuracy, but in many applications, the input source variation is beyond the designer?s control. if the entire system can be calibrated after assembly in a controlled environment (like factory test), these so urces of error are minimized if not entirely eliminated. figure 8-1 illustrates a common digital potentiometer configuration. this configuration is often referred to as a ?windowed voltage divider?. note that r 1 is not necessary to create the voltage divider, but its presence is useful when the desired threshold has limited range. it is ?windowed? because r 1 can narrow the adjustable range of v trip to a value much less than v dd ? v ss . if the output range is reduced, the magnitude of each output step is reduced. this effectively increases the trimming resolution for a fixed digital potentiometer resolution. this technique may allow a lower-cost digital potentiometer to be utilized (64 steps instead of 256 steps). the mcp4018?s low dnl performance is critical to meeting calibration accuracy in production without having to use a higher precision digital potentiometer. equation 8-1: calculating the wiper setting from the desired v trip figure 8-1: using the digital potentiometer to set a precise output voltage. 8.1.1 trimming a threshold for an optical sensor if the application has to calibrate the threshold of a diode, transistor or resistor, a variation range of 0.1v is common. often, the desired a resolution of 2 mv or better is adequate to accura tely detect the presence of a precise signal. a ?windowed? voltage divider, utilizing the mcp4018, would be a potential solution. figure 8- 2 illustrates this example application. figure 8-2: set point or threshold calibration. v trip v dd r wb r 1 r 2 + ------------------ ?? ?? = d = digital potentiomete r wiper setting (0-127) r ab = r nominal r wb = r ab ? d 127 d = ? (r 1 + r ab ) ? 127 v trip v dd v dd v out a r 1 w b mcp4018 sda scl v trip 0.1 f comparator v cc+ v cc? v dd r sense r 1 b a v dd w mcp4018 sda scl mcp6021
MCP4017/18/19 ds22147a-page 50 ? 2009 microchip technology inc. 8.2 operational amplifier applications figure 8-3 and figure 8-4 illustrate typical amplifier circuits that could replace fixed resistors with the MCP4017/18/19 to achieve digitally-adjustable analog solutions. figure 8-3: trimming offset and gain in a non-inverting amplifier. figure 8-4: programmable filter. op amp v in v out ? + r 1 b a v dd w r 3 mcp4018 MCP4017 mcp6291 op amp v in v out a b w + ? r 1 b a v dd w r 4 f c 1 2 r eq c ?? ----------------------------- = r eq r 1 r ab r wb ? + () r 2 r wb + () r w + || = thevenin equivalent mcp4018 mcp4018 mcp6021
? 2009 microchip technology inc. ds22147a-page 51 MCP4017/18/19 8.3 temperature sensor applications thermistors are resistors with very predictable variation with temp erature. thermistors are a popular sensor choice when a low-cost temperature-sensing solution is desired. unfo rtunately, thermistors have non-linear characteristics that are undesirable, typically requiring trimming in an application to achieve greater accuracy. there are several common solutions to trim & linearize thermistors. figure 8-5 and figure 8-6 are simple methods for linearizing a 3-terminal ntc thermistor. both are simple voltage dividers using a positive temperature coefficient (ptc) resistor (r 1 ) with a transfer function capable of compensating for the linearity error in the negative temperature coefficient (ntc) thermistor. the circuit, illustrated by figure 8-5 , utilizes a digital rheostat for trimming the offset error caused by the thermistor?s part-to-part vari ation. this solution puts the digital potentiometer?s r w into the voltage divider calculation. the MCP4017/18/19?s r ab temperature coefficient is a low 50 ppm (-20c to +70c). r w ?s error is substantially greater than r ab ?s error because r w varies with v dd , wiper setting and te mperature. for the 50 k devices, the error introduced by r w is, in most cases, insignificant as long as the wiper setting is > 6. for the 2 k devices, the error introduced by r w is significant because it is a higher percentage of r wb . for these reasons, the circuit illustrated in figure 8-5 is not the most optimum method for ?exciting? and linearizing a thermistor. figure 8-5: thermistor calibration using a digital potentiometer in a rheostat configuration. the circuit illustrated by figure 8-6 utilizes a digital potentiometer for trimming the offset error. this solution removes r w from the trimming equation along with the error associated with r w . r 2 is not required, but can be utilized to reduce the trimming ?window? and reduce variation due to the digital pot?s r ab part-to-part variability. figure 8-6: thermistor calibration using a digital potentiomete r in a potentiometer configuration. ntc v dd v out thermistor r 1 r 2 MCP4017 ntc v dd v out thermistor r 1 mcp4018
MCP4017/18/19 ds22147a-page 52 ? 2009 microchip technology inc. 8.4 wheatstone bridge trimming another common configuration to ?excite? a sensor (such as a strain gauge, pres sure sensor or thermistor) is the wheatstone brid ge configuration. the wheatstone bridge provides a differential output instead of a single-ended output. figure 8-7 illustrates a wheatstone bridge utilizing one to three digital potentiometers. the digital potentiometers in this example are used to trim th e offset and gain of the wheatstone bridge. figure 8-7: wheatstone bridge trimming. v dd v out 5k 50 k 50 k MCP4017 MCP4017 MCP4017
? 2009 microchip technology inc. ds22147a-page 53 MCP4017/18/19 9.0 development support 9.1 development tools to assist in your design and evaluation of the MCP4017/18/19 devices, a demo board using the MCP4017 device is in development. please check the microchip web site for the release of this board. the board part number is tentatively mcp4xxxdm-pga, and is expected to be available in the summer of 2009. 9.2 technical documentation several additional technical documents are available to assist you in your design and development. these technical documents include application notes, technical briefs, and design guides. ta b l e 9 - 1 shows some of these documents. table 9-1: technical documentation application note number title literature # an1080 understanding digital potentiome ters resistor variations ds01080 an737 using digital potentiometers to design low pass adjustable filters ds00737 an692 using a digital potentiometer to optimize a precision single supply photo detect ds00692 an691 optimizing the digital potentiometer in precision circuits ds00691 an219 comparing digital potentiometers to mechanical potentiometers ds00219 ? digital potentiometer design guide ds22017 ? signal chain design guide ds21825
MCP4017/18/19 ds22147a-page 54 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds22147a-page 55 MCP4017/18/19 10.0 packaging information 10.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e part number code mcp4019t-502e/lt benn mcp4019t-103e/lt bfnn mcp4019t-503e/lt bgnn mcp4019t-104e/lt bhnn 6-lead sc70 example: part number code part number code MCP4017t-502e/lt aenn mcp4018t-502e/lt aann MCP4017t-103e/lt afnn mcp4018t-103e/lt abnn MCP4017t-503e/lt agnn mcp4018t-503e/lt acnn MCP4017t-104e/lt ahnn mcp4018t-104e/lt adnn 5-lead sc70 xxnn example: benn xxnn aann
MCP4017/18/19 ds22147a-page 56 ? 2009 microchip technology inc.

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? 2009 microchip technology inc. ds22147a-page 57 MCP4017/18/19 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
MCP4017/18/19 ds22147a-page 58 ? 2009 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009 microchip technology inc. ds22147a-page 59 MCP4017/18/19 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
MCP4017/18/19 ds22147a-page 60 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds22147a-page 61 MCP4017/18/19 appendix a: revision history revision a (march 2009) ? original release of this document.
MCP4017/18/19 ds22147a-page 62 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds22147a-page 63 MCP4017/18/19 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: MCP4017: single rheostat with i 2 c interface MCP4017t: single rheostat with i 2 c interface (tape and reel) mcp4018: single potentiometer to gnd with i 2 c interface mcp4018t: single potentiometer to gnd with i 2 c interface (tape and reel) mcp4019: single rheostat to gnd with i 2 c interface mcp4019t: single rheostat to gnd with i 2 c interface (tape and reel) resistance version: 502 = 5 k 103 = 10 k 503 = 50 k 104 = 100 k temperature range: e = -40c to +125c package: lt = plastic small outline transistor (sc70), 5-lead, 6-lead part no. x /xx package temperature range device examples: a) MCP4017t-502e/lt: 5 k , 6-ld sc-70. b) MCP4017t-103e/lt: 10 k , 6-ld sc-70. c) MCP4017t-503e/lt: 50 k , 6-ld sc-70. d) MCP4017t-104e/lt: 100 k , 6-ld sc-70. a) mcp4018t-502e/lt: 5 k , 6-ld sc-70. b) mcp4018t-103e/lt: 10 k , 6-ld sc-70. c) mcp4018t-503e/lt: 50 k , 6-ld sc-70. d) mcp4018t-104e/lt: 100 k , 6-ld sc-70. a) mcp4019t-502e/lt: 5 k , 5-ld sc-70. b) mcp4019t-103e/lt: 10 k , 5-ld sc-70. c) mcp4019t-503e/lt: 50 k , 5-ld sc-70. d) mcp4019t-104e/lt: 100 k , 5-ld sc-70. xxx resistance version
MCP4017/18/19 ds22147a-page 64 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds22147a-page 65 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, rfpic, smartshunt and uni/o are registered trademarks of microchip te chnology incorporated in the u.s.a. and other countries. filterlab, linear active thermistor, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, nanowatt xlp, pickit, picdem, picdem.net, pictail, pic 32 logo, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, total endurance, tsharc, wiperlock and zena are trademarks of microchip te chnology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2009, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
ds22147a-page 66 ? 2009 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4080 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-6578-300 fax: 886-3-6578-370 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 03/26/09

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